It is increasingly common to transmit information from one location to another via digital transmission facilities. For example, the telephone network conventionally uses digital communication links on which is transferred data at the DS1 -digital signal level 1 - or multiple thereof. A DS1 signal is usually defined as a bipolar data stream having a 1.544 MHz frequency.
One of the problems with digital transmission is that, as the signal is transmitted along the transmission path, it traverses a plurality of regenerating stations or repeaters that cause the signal to suffer a phenomenon known as jitter. Because jitter causes the digital signal to oscillate at a lower frequency than the signal data and since the signal also carries the inherent clock or synchronization information, it is a necessary feature of any digital receiver circuit that it provides some means for minimizing the effect of jitter on the recovered data.
To this end, digital data receivers usually have an interface circuit for connection between an input port and the receiver itself. An interface circuit usually includes a data recovery circuit responsive to a bipolar data stream appearing on an input data port for reforming it into a pair of unipolar data streams, and a clock recovery circuit responsive to the pair of data streams for deriving clock signals therefrom as well as a data synchronization stage for synchronizing the received data with the recovered clock for use by subsequent digital circuitry such as a data receiver.
In the case of DS1 transmission, the data stream is a bipolar signal which is converted by the data recovery stage into a pair of unipolar signals. A logical one on the incoming DS1 signal appears as a pulse on one of the outputs of the data recovery stage, each pulse being nominally one-half of a 1.544 MHz clock cycle. A logical zero is the absence of such a pulse at the outputs of the data recovery stage.
The clock recovery stage recovers a 1.544 MHz clock signal from the incoming DS1 signal. It is therefore necessary to establish a phase relationship between the recovered clock and data to avoid data errors in the data synchronization stage. The recovered clock may have a significant amount of jitter due to the cumulative effect of the repeaters on a DS1 carrier and is also dependent on the incoming DS1 data pattern. There is consequently a certain amount of differential phase jitter between the recovered clock and received data dependent on the clock recovery technique. There must therefore be a significant amount of phase margin between the recovered clock and received data to absorb the effects of the clock-data jitter.